Semiconductor device and method
US10164053B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Aug 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method includes: forming a gate stack on a semiconductor fin, the gate stack having gate spacers along opposing sides of the gate stack; forming source/drain regions adjacent the gate stack; recessing the gate stack to form a first recess between the gate spacers; depositing a dielectric layer over the gate stack in the first recess; forming a first metal mask over the dielectric layer and the gate stack in the first recess; etching back the dielectric layer and the gate spacers to form a dielectric mask under the first metal mask; depositing a conductive material over the first metal mask and adjacent the gate stack; and planarizing the conductive material to form contacts electrically connected to the source/drain regions, top surfaces of the contacts and the dielectric mask being level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.