Memory device having a single bottom electrode layer

US10164169B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Harry-Hak-Lay Chuang · Austin, US
• Hung Cho Wang · Taipei, TW
• Tong-Chern Ong · San Jose, US
• Wen-Ting Chu
• Yu-Wen Liao · New Taipei, TW
• Kuei-Hung Shen · Hsinchu, TW
• Kuo-Yuan Tu · Baoshan, TW
• Sheng-Huang Huang · Hsinchu, TW

Key dates

• Filing date: Dec 29, 2016
• Grant date: Dec 25, 2018
• Expiry date: Dec 29, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8833

Abstract

The present disclosure relates to a method of manufacturing a memory device. The method is performed by forming an inter-layer dielectric (ILD) layer over a substrate, and forming an opening within a dielectric protection layer over the ILD layer. A bottom electrode layer is formed within the opening and over the dielectric protection layer. A chemical mechanical planarization (CMP) process is performed on the bottom electrode layer to form a bottom electrode structure having a planar upper surface and a projection that protrudes outward from a lower surface of the bottom electrode structure to within the opening. A memory element is formed over the bottom electrode structure, and a top electrode is formed over the memory element.