Switching layer scheme to enhance RRAM performance
US10164182B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2017 |
| Grant date | Dec 25, 2018 |
| Priority date | — |
| Expiry date | Jul 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/883
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an RRAM device. In some embodiments, the RRAM device includes a lower electrode disposed over a conductive lower interconnect layer. An upper electrode is over the lower electrode and a multi-layer data storage structure is between the lower and upper electrodes. The multi-layer data storage structure has first and second sub-layers. The first sub-layer has a first metal from a first group of metals, a first concentration of a second metal from a second group of metals, and oxygen. The second sub-layer has a third metal from the first group of metals, a non-zero second concentration of a fourth metal from a second group of metals, and oxygen. The non-zero second concentration is smaller than the first concentration and causes conductive filaments formed within the second sub-layer to be wider than conductive filaments formed within the first sub-layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.