Hardware node having a matrix vector unit with block-floating point processing
US10167800B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Aug 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processors and methods for neural network processing are provided. A method includes receiving vector data corresponding to a layer of a neural network model, where each of the vector data has a value comprising at least one exponent. The method further includes first processing a first subset of the vector data to determine a first shared exponent for representing values in the first subset of the vector data in a block-floating point format and second processing a second subset of the vector data to determine a second shared exponent for representing values in the second subset of the vector data in a block-floating point format in a manner that no vector data from the second subset of the vector data influences a determination of the first shared exponent and no vector data from the first subset of the vector data influences a determination of the second shared exponent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.