Read buffer architecture supporting integrated XOR-reconstructed and read-retry for non-volatile random access memory (NVRAM) systems
US10169145B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2016 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | May 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a method includes issuing a read request to read one or more units of data from at least one non-volatile random access memory (NVRAM) device. The read request includes one or more read voltage thresholds. The method also includes receiving the one or more data units and read command parameters used to read the one or more data units from the at least one NVRAM device. Moreover, the method includes storing error-free data units, the read command parameters used to read the error-free data units from the at least one NVRAM device, and a read completion status to one of a plurality of read buffers. The read completion status indicates a completed read when a data unit is error-free and indicates an incomplete read when a data unit is errored.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.