Multi-topology logic gates
US10169617B2 · kind B2 · utility
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Key dates
| Filing date | Apr 29, 2015 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Oct 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/034
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An RMTL gate includes at least two logic blocks, where at least one of the logic blocks operates in multiple modes. The respective logic block mode(s) are selected by a topology selector which applies mode control signals to the logic blocks in order to obtain a selected topology for logic circuit operation. RMTL logic gates may be cascaded and/or interconnected to form an RMTL logic circuit with multiple logic gates which may operate with dynamically varying topologies. Use of random, semi-random or specified control sequences may protect the logic circuit against security attacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.