Data transmission apparatus for memory and data transmission method thereof
US10170166B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Sep 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The data transmission apparatus includes a prior stage shift register circuit and a plurality of rear stage shift register circuits. The prior stage shift register circuit is coupled to a sense amplifying device of the memory, receives sensed data from the sense amplifying device and outputs a plurality of the readout data in series by bitwise shifting out the sensed data according to a shift clock signal. The plurality of rear stage shift register circuits are coupled to the prior stage shift register circuit and respectively coupled to a plurality of pads. The plurality of rear stage shift register circuits respectively receive the readout data and respectively bitwise transport the readout data to the pads according to a clock signal. Wherein, a frequency of the shift clock signal is less than a frequency of the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.