Advanced chip to wafer stacking
US10170447B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Nov 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips, where the first chips are on a first substrate; forming a second bonding layer on a second wafer and second chips, where the second chips are on a second substrate; separating the second chips from the second wafer, wherein a portion of the second bonding layer remains on the second chips; moving the separated second chips to a cleaning chamber using a vacuum chuck; cleaning the separated second chips in the cleaning chamber; and bonding the second bonding layer on the separated second chips to the first bonding layer on the first chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.