Method for bonding and interconnecting integrated circuit devices
US10170450B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Sep 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for bonding and interconnecting two or more IC devices arranged on substrates such as silicon wafers is disclosed. In one aspect, the wafers are bonded by a direct bonding technique to form a wafer assembly, and the multiple IC devices are provided with metal contact structures. At least the upper substrate is provided prior to bonding with a cavity in its bonding surface. A TSV (Through Semiconductor Via) is produced through the bonded wafer assembly and an aggregate opening is formed including the TSV opening and the cavity. After the formation of an isolation liner on at least part of the sidewalls of the aggregate opening (that is, at least on the part where the liner isolates the aggregate opening from semiconductor material), a TSV interconnection plug is produced in the aggregate opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.