Semiconductor devices with enhanced deterministic doping and related methods
US10170560B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 21, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Jun 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region, and performing an anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.