Semiconductor device and fabrication method thereof
US10170573B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Oct 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate, a metal gate on the substrate, and a first inter-layer dielectric (ILD) layer around the metal gate. A top surface of the metal gate is lower than a top surface of the ILD layer thereby forming a recessed region atop the metal gate. A mask layer is disposed in the recessed region. A void is formed in the mask layer within the recessed region. A second ILD layer is disposed on the mask layer and the first ILD layer. A contact hole extends into the second ILD layer and the mask layer. The contact hole exposes the top surface of the metal gate and communicates with the void. A conductive layer is disposed in the contact hole and the void.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.