Uniform bottom spacer for vertical field effect transistor
US10170582B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Sep 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor structure includes forming a protective liner comprising a metal oxide above and in direct contact with a semiconductor substrate, a fin extending upward from the semiconductor substrate and a NON hardmask positioned on top of the fin, removing the protective liner from top surfaces of the semiconductor substrate and NON hardmask, the protective liner remaining on sidewalls of the fin and the NON hardmask, depositing a first dielectric layer, simultaneously removing top portions of the first dielectric layer and NON hardmask, the first dielectric layer remains in direct contact with a bottom portion of the protective liner and the semiconductor substrate, removing the protective liner, the removing of the protective liner creates an opening between the first dielectric layer and the bottom portion of the fin that is subsequently filled with a second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.