Inventor · Hopewell Junction, NY, US

Michael P. Belyansky

58Patents
10h-index
87Co-inventors
81Inventor score

Filing activity: Aug 23, 2001 → Nov 17, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US6977194B2 Structure and method to improve channel mobility by gate electrode stress modification Electricity 180 Expired
US7273638B2 High density plasma oxidation Electricity 37 Expired
US6562713B1 Method of protecting semiconductor areas while exposing a gate Electricity 23 Expired
US7585704B2 Method of producing highly strained PECVD silicon nitride thin films at low temperature Electricity 22 Expired
US6982196B2 Oxidation method for altering a film structure and CMOS transistor structure formed therewith Electricity 19 Expired
US6869860B2 Filling high aspect ratio isolation structures with polysilazane based material Electricity 18 Expired
US6890833B2 Trench isolation employing a doped oxide trench fill Electricity 15 Expired
US7691701B1 Method of forming gate stack and structure thereof Electricity 13 Active
US9929012B1 Resist having tuned interface hardmask layer for EUV exposure Electricity 12 Active
US7202516B2 CMOS transistor structure including film having reduced stress by exposure to atomic oxygen Electricity 11 Expired
US7271049B2 Method of forming self-aligned low-k gate cap Electricity 9 Active
US6642147B2 Method of making thermally stable planarizing films Electricity 8 Expired
US6914015B2 HDP process for high aspect ratio gap filling Electricity 8 Expired
US7659160B2 Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabrication same Electricity 7 Active
US7230296B2 Self-aligned low-k gate cap Electricity 6 Expired
US10249730B1 Controlling gate profile by inter-layer dielectric (ILD) nanolaminates Electricity 6 Active
US7205206B2 Method of fabricating mobility enhanced CMOS devices Electricity 5 Expired
US9397002B1 Self-aligned punchthrough stop doping in bulk finFET by reflowing doped oxide Electricity 5 Active
US7648871B2 Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabricating same Electricity 5 Active
US7342266B2 Field effect transistors with dielectric source drain halo regions and reduced miller capacitance Emerging Cross-Sectional Technologies 4 Expired
US7122849B2 Stressed semiconductor device structures having granular semiconductor material Electricity 4 Expired
US10388766B2 Vertical transport FET (VFET) with dual top spacer Electricity 4 Active
US10170582B1 Uniform bottom spacer for vertical field effect transistor Electricity 3 Active
US8557649B2 Method for controlling structure height Electricity 3 Active
US10741663B1 Encapsulation layer for vertical transport field-effect transistor gate stack Electricity 3 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.