Nanosheet substrate isolated source/drain epitaxy by dual bottom spacer
US10170638B1 · kind B1 · utility
35Cited by
2References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 23, 2018 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Jan 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by providing a dual bottom spacer structure on physically exposed surfaces of a semiconductor substrate after formation of a nanosheet stack of alternating nanosheets of a sacrificial semiconductor material nanosheet and a semiconductor channel material nanosheet on a portion of the semiconductor substrate. The presence of the dual bottom spacer structure prevents bottom up growth of the semiconductor material that provides the S/D regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.