Inventor · Troy, NY, US

Alexander Reznicek

1,279Patents
29h-index
208Co-inventors
93Inventor score

Filing activity: Oct 29, 2003 → Aug 10, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US9799736B1 High acceptor level doping in silicon germanium Electricity 398 Active
US8895395B1 Reduced resistance SiGe FinFET devices and method of forming same Electricity 312 Active
US8969934B1 Gate-all-around nanowire MOSFET and method of formation Electricity 308 Active
US7772096B2 Formation of SOI by oxidation of silicon with engineered porosity gradient Electricity 196 Active
US9837414B1 Stacked complementary FETs featuring vertically stacked horizontal nanowires Electricity 105 Active
US7968459B2 Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors Emerging Cross-Sectional Technologies 102 Active
US9653289B1 Fabrication of nano-sheet transistors with different threshold voltages Electricity 96 Active
US7125785B2 Mixed orientation and mixed material semiconductor-on-insulator wafer Electricity 85 Expired
US7087965B2 Strained silicon CMOS on hybrid crystal orientations Electricity 84 Expired
US7023055B2 CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding Electricity 79 Expired
US9443982B1 Vertical transistor with air gap spacers Electricity 71 Active
US9659963B2 Contact formation to 3D monolithic stacked FinFETs Electricity 70 Active
US9570551B1 Replacement III-V or germanium nanowires by unilateral confined epitaxial growth Electricity 67 Active
US9716158B1 Air gap spacer between contact and gate region Electricity 67 Active
US9773913B1 Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance Electricity 62 Active
US9525064B1 Channel-last replacement metal-gate vertical field effect transistor Electricity 53 Active
US8796093B1 Doping of FinFET structures Electricity 52 Active
US9954058B1 Self-aligned air gap spacer for nanosheet CMOS devices Electricity 47 Active
US9287135B1 Sidewall image transfer process for fin patterning Electricity 44 Active
US9741626B1 Vertical transistor with uniform bottom spacer formed by selective oxidation Electricity 42 Active
US9293459B1 Method and structure for improving finFET with epitaxy source/drain Electricity 39 Active
US9190471B2 Semiconductor structure having a source and a drain with reverse facets Electricity 35 Active
US10170638B1 Nanosheet substrate isolated source/drain epitaxy by dual bottom spacer Electricity 35 Active
US9589845B1 Fin cut enabling single diffusion breaks Electricity 34 Active
US8900951B1 Gate-all-around nanowire MOSFET and method of formation Electricity 32 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.