3D memory
US10170639B2 · kind B2 · utility
10Cited by
18References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2016 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Jan 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.