System and method for a high-ohmic resistor
US10171916B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2016 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Aug 24, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04R2410/03
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to an embodiment, a circuit includes a high-Ω resistor including a plurality of semiconductor junction devices coupled in series and a plurality of additional capacitances formed in parallel with the plurality of semiconductor junction devices. Each semiconductor junction device of the plurality of semiconductor junction devices includes a parasitic doped well capacitance configured to insert a parasitic zero in a noise transfer function of the high-Ω resistor. Each additional capacitance of the plurality of additional capacitances is configured to adjust a parasitic pole in the noise transfer function of the high-Ω resistor in order to compensate for the parasitic zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.