Techniques for adjusting latency of a clock signal to affect supply voltage
US10175734B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2016 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Feb 16, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes circuit blocks, a clock network coupled to the circuit blocks, and a supply voltage network coupled to the circuit blocks. Each of the circuit blocks comprises at least one clocked circuit that receives a clock signal. The clock network provides the clock signal to the clocked circuits in the circuit blocks. The supply voltage network provides a supply voltage to the circuit blocks. A latency of the clock signal provided through the clock network to at least one of the circuit blocks is adjusted to decrease a peak voltage drop in the supply voltage caused by a peak current drawn by the circuit blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.