VLIW type instruction packet structure and processor suitable for processing such an instruction packet
US10175989B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2015 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Dec 16, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor including multiple processing units for processing multiple elementary instructions in parallel, the elementary instructions including one or more syllables, each having a rank in the elementary instruction, and an input circuit configured to receive an instruction bundle including multiple elementary instructions, and to transmit to the processing units all syllables of first rank of the elementary instructions of the instruction bundle before syllables of second rank of the elementary instructions of the instruction bundle, the syllables of same rank being ordered according to the target processing unit of each syllable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.