Kalray
🏢 View company profile →22Patents
22Active
22Granted
46Portfolio score
Filing activity: Jul 6, 2010 → Dec 29, 2021
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8619622B2 | Network on chip with quality of service | Electricity | 41 | Active |
| US9565122B2 | Stream management in an on-chip network | Electricity | 3 | Active |
| US9851977B2 | Apparatus and method for combining thread warps with compatible execution masks for simultaneous execution and increased lane utilization | Physics | 3 | Active |
| US9898251B2 | Bit-matrix multiplication using explicit register | Physics | 1 | Active |
| US10915488B2 | Inter-processor synchronization system | Physics | 1 | Active |
| US12141626B2 | Configurable inter-processor synchronization system | Physics | 1 | Active |
| US8593818B2 | Network on chip building bricks | Physics | 1 | Active |
| US11144480B2 | Atomic instruction having a local scope limited to an intermediate cache level | Physics | 1 | Active |
| US11489544B2 | Fast CRC computation circuit using an on-the-fly reconfigurable generator polynomial | Electricity | 0 | Active |
| US11550544B2 | Fused Multiply-Add operator for mixed precision floating-point numbers with correct rounding | Physics | 0 | Active |
| US11995218B2 | Processor with a configurable distribution of privileged resources and exceptions between protection rings | Physics | 0 | Active |
| US11604646B2 | Processor comprising a double multiplication and double addition operator actuable by an instruction with three operand references | Physics | 0 | Active |
| US10250697B2 | Token bucket flow-rate limiter | Electricity | 0 | Active |
| US9766951B2 | Hardware synchronization barrier between processing units | Physics | 0 | Active |
| US9367287B2 | Mixed precision fused multiply-add operator | Physics | 0 | Active |
| US11294627B2 | Floating point dot-product operator with correct rounding | Physics | 0 | Active |
| US10175989B2 | VLIW type instruction packet structure and processor suitable for processing such an instruction packet | Physics | 0 | Active |
| US8503466B2 | Network on chip input/output nodes | Physics | 0 | Active |
| US10484514B2 | Method for dispatching network frames among processing resources | Electricity | 0 | Active |
| US11169808B2 | Blockwise matrix multiplication system | Physics | 0 | Active |
| US9064092B2 | Extensible network-on-chip | Physics | 0 | Active |
| US9813348B2 | System for transmitting concurrent data flows on a network | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.