Patent · US Active

Using data pattern to mark cache lines as invalid

US10176099B2 · kind B2 · utility

2Cited by

2References

21Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Jayesh Gaur · Bengaluru, IN
Supratik Majumder · Bengaluru, IN
Zvika Greenfield · Kfar Sava, IL
Israel Diamand · Lod, IL

Key dates

Filing date	Jul 11, 2016
Grant date	Jan 8, 2019
Priority date	—
Expiry date	Jul 11, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/621
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus includes a cache controller, the cache controller to receive, from a requestor, a memory access request referencing a memory address of a memory. The cache controller may identify a cache entry associated with the memory address, and responsive to determining that a first data item stored in the cache entry matches a data pattern indicating cache entry invalidity, read a second data item from a memory location identified by the memory address. The cache controller may then return, to the requestor, a response comprising the second data item.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.