Methods and systems for dynamic DRAM cache sizing
US10176107B2 · kind B2 · utility
1Cited by
8References
19Claims
0Family size
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Key dates
| Filing date | Mar 29, 2014 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Jun 9, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques described herein generally include methods and systems related to dynamic cache-sizing used to reduce the energy consumption of a DRAM cache in a chip multiprocessor. Dynamic cache sizing may be performed by adjusting the refresh interval of a DRAM cache or by combining way power-gating of the DRAM cache with adjusting the refresh interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.