Inventor · Raleigh, NC, US

Yan Solihin

57Patents
4h-index
6Co-inventors
55Inventor score

Filing activity: Mar 20, 2009 → Sep 9, 2019

Most-cited inventions

PatentTitleAreaCited byStatus
US9158689B2 Aggregating cache eviction notifications to a directory Emerging Cross-Sectional Technologies 6 Active
US8195888B2 Multiprocessor cache prefetch with off-chip bandwidth allocation Physics 6 Active
US9846627B2 Systems and methods for modeling memory access behavior and memory traffic timing behavior Physics 5 Active
US8244986B2 Data storage and access in multi-core processor architectures Physics 5 Active
US9047137B2 Balanced processing using heterogeneous cores Emerging Cross-Sectional Technologies 4 Active
US9766681B2 Operations related to a retransmission buffer Emerging Cross-Sectional Technologies 3 Active
US9304946B2 Hardware-base accelerator for managing copy-on-write of multi-level caches utilizing block copy-on-write differential update table Physics 3 Active
US8615633B2 Multi-core processor cache coherence for reduced off-chip traffic Physics 3 Active
US8874849B2 Sectored cache with a tag structure capable of tracking sectors of data stored for a particular cache way Emerging Cross-Sectional Technologies 3 Active
US9053057B2 Cache coherence directory in multi-processor architectures Emerging Cross-Sectional Technologies 2 Active
US9710303B2 Shared cache data movement in thread migration Emerging Cross-Sectional Technologies 2 Active
US9772950B2 Multi-granular cache coherence Physics 2 Active
US9304898B2 Hardware-based array compression Emerging Cross-Sectional Technologies 2 Active
US9275696B2 Energy conservation in a multicore chip Emerging Cross-Sectional Technologies 2 Active
US9098406B2 Managing addressable memory in heterogeneous multicore processors Physics 2 Active
US9229865B2 One-cacheable multi-core architecture Physics 2 Active
US9760486B2 Accelerating cache state transfer on a directory-based multicore architecture Physics 1 Active
US9465729B2 Memory allocation accelerator Physics 1 Active
US8924754B2 Quality of service targets in multicore processors Emerging Cross-Sectional Technologies 1 Active
US9990293B2 Energy-efficient dynamic dram cache sizing via selective refresh of a cache in a dram Emerging Cross-Sectional Technologies 1 Active
US8667227B2 Domain based cache coherence protocol Physics 1 Active
US11281545B2 Methods of crash recovery for data stored in non-volatile main memory Physics 1 Active
US8589933B2 Low power execution of a multithreaded program Emerging Cross-Sectional Technologies 1 Active
US10176107B2 Methods and systems for dynamic DRAM cache sizing Emerging Cross-Sectional Technologies 1 Active
US8990828B2 Resource allocation in multi-core architectures Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.