Multi-packet processing with ordering rule enforcement
US10176135B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2017 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | May 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes an input/output adapter operable to receive a plurality of packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet at a data link layer and determine a state of a first output indicator to maintain packet ordering. Based on determining that a first receiver formatting interface is selected by the first output indicator, the controller performs an alignment adjustment and output of the first packet by the first receiver formatting interface. Based on determining that a second receiver formatting interface is selected by the first output indicator, the controller performs the alignment adjustment and output of the first packet by the second receiver formatting interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.