Recap layer scheme to enhance RRAM performance
US10176866B1 · kind B1 · utility
11Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2017 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Oct 25, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An RRAM device is disclosed. The RRAM device includes a lower electrode structure over a conductive lower interconnect layer, an upper electrode structure over the lower electrode structure, and a switching layer between the lower electrode and the upper electrode structure. The switching layer has switching layer outer sidewalls. The RRAM device also includes a recap layer having a vertical portion that extends vertically from corners of the switching layer along the upper electrode sidewalls. The recap layer has a horizontal portion that extends horizontally from the corners to the switching layer outer sidewalls.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.