Semiconductor packages and methods of manufacturing the same
US10177131B2 · kind B2 · utility
0Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2017 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Mar 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, an interconnect substrate spaced apart from the semiconductor chip on the substrate and including a conductive member therein, a solder ball on the interconnect substrate and electrically connected to the conductive member, a polymer layer on the interconnect substrate and the semiconductor chip and including an opening through which the solder ball is exposed, and polymer particles in the solder ball and including the same material as the polymer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.