Layout pattern for SRAM and manufacturing methods thereof
US10177132B2 · kind B2 · utility
6Cited by
22References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 1, 2016 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Dec 3, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout pattern of a static random access memory, including a first inverter and a second inverter constituting a latch circuit. A first inner access transistor, a second inner access transistor, a first outer access transistor and a second outer access transistor are electrically connected to the latch circuit, wherein the first outer access transistor has a first gate length, the first inner access transistor has a second gate length, and the first gate length is different from the second gate length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.