Methods of forming package structures for enhanced memory capacity and structures formed thereby
US10177161B2 · kind B2 · utility
3Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2016 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Dec 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/17181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.