Circuit board stacked structure and method for forming the same
US10178755B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2017 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | May 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/041
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit board includes a first dielectric layer, a first circuit layer, a second circuit layer, a plurality of conductive vias, a second dielectric layer, a patterned seed layer, and a plurality of bonding layers. The first circuit layer is disposed in the first dielectric layer. The second circuit layer is disposed on the first dielectric layer. The conductive vias are disposed in the first dielectric layer and connect the first circuit layer to the second circuit layer. The second dielectric layer is disposed on the first dielectric layer and the second circuit layer and has a plurality of openings to expose a plurality of parts of the second circuit layer. The patterned seed layer is disposed on the exposed parts of second circuit layer and sidewalls of the openings. The bonding layers are respectively disposed on the patterned seed layer and made of porous copper.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.