Sense amplifier with bit line pre-charge circuit for reading flash memory cells in an array
US10181354B2 · kind B2 · utility
3Cited by
5References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2017 |
| Grant date | Jan 15, 2019 |
| Priority date | — |
| Expiry date | Aug 29, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to an improved sense amplifier for reading values in flash memory cells in an array. In one embodiment, a sense amplifier comprises an improved pre-charge circuit for pre-charging a bit line during a pre-charge period to increase the speed of read operations. In another embodiment, a sense amplifier comprises simplified address decoding circuitry to increase the speed of read operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.