Patent · US Active

Layout effect mitigation in FinFET

US10181403B2 · kind B2 · utility

0Cited by

7References

8Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Da Yang · San Diego, US
Yanxiang Liu · San Diego, US
Jun Yuan · San Diego, US
Kern Rim · Yorktown Heights, US

Key dates

Filing date	Mar 2, 2018
Grant date	Jan 15, 2019
Priority date	—
Expiry date	Mar 2, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/038

Abstract

Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.