Inventor · San Diego, CA, US

Da Yang

25Patents

3h-index

37Co-inventors

59Inventor score

Filing activity: Mar 4, 2009 → Jun 8, 2020

Most-cited inventions

Patent	Title	Area	Cited by	Status
US9871121B2	Semiconductor device having a gap defined therein	Electricity	22	Active
US9799560B2	Self-aligned structure	Electricity	13	Active
US9953979B2	Contact wrap around structure	Electricity	7	Active
US9653399B2	Middle-of-line integration methods and semiconductor devices	Electricity	3	Active
US10497702B2	Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells	Electricity	3	Active
US10043796B2	Vertically stacked nanowire field effect transistors	Electricity	3	Active
US9985014B2	Minimum track standard cell circuits for reduced area	Electricity	3	Active
US9620454B2	Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods	Electricity	2	Active
US9397007B2	Method for manufacturing semiconductor structure through forming an additional layer inside opening of a photoresist layer	Electricity	2	Active
US10090244B2	Standard cell circuits employing high aspect ratio voltage rails for reduced resistance	Electricity	2	Active
US8669160B2	Method for manufacturing a semiconductor device	Electricity	1	Active
US10032678B2	Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices	Electricity	1	Active
US8420492B2	MOS transistor and method for forming the same	Electricity	1	Active
US9263279B2	Combining cut mask lithography and conventional lithography to achieve sub-threshold pattern features	Electricity	1	Active
US10079293B2	Semiconductor device having a gap defined therein	Electricity	1	Active
US9997360B2	Method for mitigating layout effect in FINFET	Electricity	1	Active
US9502283B2	Electron-beam (E-beam) based semiconductor device features	Electricity	0	Active
US9245971B2	Semiconductor device having high mobility channel	Electricity	0	Active
US10763364B1	Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods	Electricity	0	Active
US9859210B2	Integrated circuits having reduced dimensions between components	Electricity	0	Active
US10181403B2	Layout effect mitigation in FinFET	Electricity	0	Active
US7989804B2	Test pattern structure	Emerging Cross-Sectional Technologies	0	Active
US11152347B2	Cell circuits formed in circuit cells employing offset gate cut areas in a non-active area for routing transistor gate cross-connections	Electricity	0	Active
US10700204B2	Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods	Electricity	0	Active
US10559501B2	Self-aligned quadruple patterning process for Fin pitch below 20nm	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.