Patent · US Active

Systems and methods for statistical static timing analysis

US10185795B1 · kind B1 · utility

8Cited by

3References

20Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Igor Keller · Pleasanton, US
Praveen Ghanta · Cupertino, US
Arun Kumar Mishra · Noida, IN

Key dates

Filing date	Oct 11, 2016
Grant date	Jan 22, 2019
Priority date	—
Expiry date	Dec 10, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Electronic design automation systems, methods, and media are presented for characterizing on-chip variation of circuit elements in a circuit design using statistical values including skew, and for performing statistical static timing analysis using these statistical values. One embodiment models delay characteristics under certain operating conditions for circuit elements with asymmetric (e.g., non-Gaussian) probability density functions using normalized skewness. The modeled delay can then be used to perform various timing analysis operations.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.