Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
US10186480B2 · kind B2 · utility
5Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2013 |
| Grant date | Jan 22, 2019 |
| Priority date | — |
| Expiry date | May 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.