Semiconductor device having metal gate
US10186594B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 4, 2017 |
| Grant date | Jan 22, 2019 |
| Priority date | — |
| Expiry date | Jul 4, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.