Silicon carbide (SiC) MOSFET with a silicon oxide layer capable of suppressing deterioration of carrier mobility and variation in threshold voltage
US10186596B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | May 4, 2017 |
| Grant date | Jan 22, 2019 |
| Priority date | — |
| Expiry date | May 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device according to an embodiment includes a silicon carbide layer, a gate electrode, and a silicon oxide layer disposed between the silicon carbide layer and the gate electrode, a number of single bonds between carbon atoms being larger than that of double bonds between carbon atoms in the silicon oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.