Memory systems and operation method thereof
US10191807B2 · kind B2 · utility
0Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2017 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Jul 16, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2906
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The memory system includes a BCH error correction circuit suitable for generating a BCH error correction code using a first write data which is a portion of a write data from a host, a Hamming error correction circuit suitable for generating a Hamming error correction code using a second write data which is a remaining portion of the write data, a plurality of first memory devices suitable for storing first write data and the BCH error correction code, and one or more second memory devices suitable for storing the second write data and the Hamming error correction code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.