Patent · US Active

Safe double buffering using DMA safe linked lists

US10191871B2 · kind B2 · utility

2Cited by

14References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Simon Cottam · Bristol, GB
Patrice Woodward · Chipping Sodbury, GB

Key dates

Filing date	Jun 20, 2017
Grant date	Jan 29, 2019
Priority date	—
Expiry date	Jun 20, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/1642
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In some embodiments, a DMA controller includes a set of transaction control registers configured to receive a linked list sequence of transaction control sets. The transaction control sets collectively describe a data transfer by which the DMA controller is to move data from a peripheral alternatingly to a first memory buffer and a second memory buffer, wherein the first and second memory buffers are arranged in parallel with one another at an interface of the peripheral. The DMA controller is configured to transfer a first set of data from the peripheral to the first memory buffer according to a first transaction control set in the linked list sequence, and is configured to subsequently transfer a second set of data from the peripheral to the second buffer according to a second transaction control set in the linked list sequence.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.