Inter-integrated circuit bus arbitration system capable of avoiding host conflict
US10191883B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 22, 2017 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Apr 13, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An inter-integrated circuit bus arbitration system includes a first master circuit, a second master circuit, an analog switch circuit, an initial state identification circuit, and a selection control circuit. When the first master circuit is initiated to transmit data, the initial state identification circuit generates a first initial pulse signal. When the second master circuit is initiated to transmit data, the initial state identification circuit generates a second initial pulse signal. If the first initial pulse signal leads the second initial pulse signal, the selection control circuit generates a first control signal to make the analog switch circuit establish electrical connections between the first master circuit and an external data line and an external clock line when receiving the first control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.