Memory instruction pipeline with an additional write stage in a memory device that uses dynamic redundancy registers
US10192601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2017 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Dec 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1693
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory pipeline for performing a write operation in a memory device is disclosed. The memory pipeline comprises an input register operable to receive a first data word and an associated address to be written into a memory bank. The pipeline also comprises a first write register of a first pipe-stage coupled to the input register and operable to receive the first data word and the associated address from the input register, wherein the first write register is further operable to perform a first attempt at writing said data word into the memory bank. Further, the pipeline comprises a second write register of the second pipe-stage coupled to the first write register and operable to receive the first data word and the associated address from the first write register, wherein the second write register is further operable to perform a second attempt at writing the first data word into the memory bank at the location corresponding to the associated address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.