Methodology for chamber performance matching for semiconductor equipment
US10192763B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2015 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Jan 6, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide methodology to match and calibrate processing chamber performance in a processing chamber. In one embodiment, a method for calibrating a processing chamber for semiconductor manufacturing process includes performing a first predetermined process in a processing chamber, collecting a first set of signals transmitted from a first group of sensors disposed in the processing chamber to a controller while performing the predetermined process, analyzing the collected first set of signals, comparing the collected first set of signals with database stored in the controller to check sensor responses from the first group of sensors, calibrating sensors based on the collected first set of signals when a mismatch sensor response is found, subsequently performing a first series of processes in the processing chamber, and collecting a second set of signals transmitted from the sensors to the controller while performing the series of processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.