Semiconductor package and electronic device having heat dissipation pattern and/or heat conducting line
US10192855B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2015 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Oct 6, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package is provided. The semiconductor package include a lower semiconductor package including a lower package substrate and a lower semiconductor chip mounted thereon, and an upper semiconductor package provided on the lower semiconductor package to include an upper package substrate and an upper semiconductor chip mounted thereon. The upper package substrate include an upper heat-dissipation pattern, the lower semiconductor chip include a first via connected to the upper heat-dissipation pattern through the lower semiconductor chip, and the first via may provide a pathway for dissipating heat generated in the lower semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.