Nonvolatile memory cell and fabrication method thereof
US10192874B2 · kind B2 · utility
4Cited by
13References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 19, 2017 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Jun 19, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A nonvolatile memory cell includes a substrate having a drain region, a source region, and a channel region between the drain region and the source region. A floating gate and a select gate are disposed on the channel region. A control gate is disposed on the floating gate. An erase gate is disposed on the source region. The erase gate includes a lower end portion that extends into a major surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.