Three-dimensional memory devices having through-stack contact via structures and method of making thereof
US10192929B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 24, 2017 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Mar 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76831
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional memory device includes conductive structures located over a substrate, an alternating stack of insulating layers and electrically conductive layers formed over the conductive structures, and an array of memory structures formed through the alternating stack. Each of the memory structures includes memory elements located at levels of the electrically conductive layers. A contact region can be formed on the alternating stack. Two-stage contact via cavities having a greater width above a top surface of a respective electrically conductive layer and having a narrower width through the alternating stack can be formed in the contact region. Upper insulating spacers and lower insulating spacers are formed such that annular surfaces of the respective electrically conductive layer are physically exposed. Two-stage contact via structures can provide electrical contact between the electrically conductive layers and the conductive structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.