Composite gate dielectric layer applied to group III-V substrate and method for manufacturing the same
US10192963B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2015 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Jul 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a composite gate dielectric layer for a Group III-V substrate and a method for manufacturing the same. The composite gate dielectric layer comprises: an AlxY2-xO3 interface passivation layer formed on the group III-V substrate; and a high dielectric insulating layer formed on the AlxY2-xO3 interface passivation layer, wherein 1.2≤x≤1.9. The composite gate dielectric layer modifies the Al/Y ratio of the AlxY2-xO3 interface passivation layer, changes the average number of atomic coordination in the AlxY2-xO3 interface passivation layer, and decreases the interface state density and boundary trap density of the Group III-V substrate, increases the mobility of the MOS channel. By cooperation of the AlxY2-xO3 interface passivation layer and high dielectric insulation layer, it reduces leakage current and improves tolerance of the dielectric layer on the voltage, and improves the quality of the MOS capacitor of the Group III-V substrate and enhances its reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.