LDMOS with adaptively biased gate-shield
US10192983B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2017 |
| Grant date | Jan 29, 2019 |
| Priority date | — |
| Expiry date | Mar 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/126
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.