High K scheme to improve retention performance of resistive random access memory (RRAM)

US10193065B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Trinh Hai Dang · Hsinchu, TW
• Hsing-Lien Lin · Hsinchu, TW
• Chin-Wei Liang · Hengshan, TW
• Cheng-Yuan Tsai · Taipei, TW
• Chia-Shiung Tsai · Jinshanmian, TW

Key dates

• Filing date: Aug 28, 2014
• Grant date: Jan 29, 2019
• Expiry date: Jul 14, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/826

Abstract

An integrated circuit or semiconductor structure of a resistive random access memory (RRAM) cell is provided. The RRAM cell includes a bottom electrode and a data storage region having a variable resistance arranged over the bottom electrode. Further, the RRAM cell includes a diffusion barrier layer arranged over the data storage region, an ion reservoir region arranged over the diffusion barrier layer, and a top electrode arranged over the ion reservoir region. A method for manufacture the integrated circuit or semiconductor structure of the RRAM cell is also provided.