Patent · US Active

Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems

US10193203B2 · kind B2 · utility

2Cited by
201References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 3, 2018
Grant dateJan 29, 2019
Priority date—
Expiry dateJan 3, 2038

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH05K1/00
  • WIPO fieldTelecommunications
  • WIPO sectorElectrical engineering

Abstract

Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.