Digital low drop-out regulator and operation method thereof
US10198015B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 11, 2018 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Jun 11, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A digital LDO regulator includes: a pulse control circuit for generating a proportional control signal based on an error code, generating an integral control signal that toggles during a first section, which includes an initialization section and an integration section, based on the proportional control signal, and generating a state information signal that defines a steady state section, the initialization section, and the integration section; a proportional control circuit for outputting a first drive signal by multiplying the error code by a proportional gain factor based on the proportional control signal; an integral control circuit for outputting a second drive signal by multiplying the error code by an integral gain factor based on the state information signal and the integral control signal; and a driver for adjusting the output voltage in response to the first drive signal and the second drive signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.