Flexible framework to support memory synchronization operations
US10198261B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2016 |
| Grant date | Feb 5, 2019 |
| Priority date | — |
| Expiry date | Sep 20, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing memory synchronization operations is provided that includes receiving, at a programmable cache controller in communication with one or more caches, an instruction in a first language to perform a memory synchronization operation of synchronizing a plurality of instruction sequences executing on a processor, mapping the received instruction in the first language to one or more selected cache operations in a second language executable by the cache controller and executing the one or more cache operations to perform the memory synchronization operation. The method further comprises receiving a second mapping that provides mapping instructions to map the received instruction to one or more other cache operations, mapping the received instruction to one or more other cache operations and executing the one or more other cache operations to perform the memory synchronization operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.